# Blog Archives

## VHDL when else vs. case is

I recently i tried to compress some random numbers. 😉 The idea was to use hierarachical state maschine to generate the random looking data from them. To do this i would need to generate the transistion logic of the state maschinne out of the random data. I thought KV-Diagramms or the quine mccluskey algorithm should work since they minimize the logic function.

As i know modern synthesis tools use these technics, so i just thought, why not put the combinatorical transition logic of some random numbers into a vhdl description and see how many LUT4’s (each 16 bits) it would take.

What i ended up doing was compering and wondering the synthesis result between the VHDL:

when else statment and the case is statment. (Results in the next blog)