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VHDL when else vs. case is (part 2)

Ok there are two implementations. The implementation basically does a data mapping of 88 random 11 bit wide  indata values to 88, 11 bit wide outdata values. Everything is done combinatorically.

The first implemntation looks like this:

p1: process(indata)
begin
case indata is
when “11100000001” => outdata<=”10000110111″;

when “10000110111” => outdata<=”00001011001″;

…….(86 more mappings)

when others => outdata<=”———–“;
end case;
end process;

And the second one implents the same thing with exactly the same numbers but uses an alternative statement:

outdata <= “10000110111” when indata=”11100000001″ else
“00001011001” when indata=”10000110111″ else

………………(85 more mappings)

“11110110011” when indata=”00001000001″ else
“———–“;

 

To make the story short, here is the result from Quartus v11.1 :

First implemntation with case is:

Total logic elements : 261 / 33,216 ( < 1 % )

 

Second implemntation with when else:

Total logic elements : 932 / 33,216 ( 3 % )

 

Yes thats quite creapy. Thats nearly 4 times as much logic.

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